I want to make a Schmitt trigger for a signal, X, who's thresholds are set by two voltages, A and B.
I think I'm having a brain fart. I don't think it's possible to do this with just a single comparator and some resistors, but It would be interesting to know what simplified options there are to do this.
My inelegant half-solution is below:
simulate this circuit – Schematic created using CircuitLab
Perhaps assume that A is always greater than B, but otherwise they may be any value.
Something along these lines MAY meet your specification.
I'll not develop the cct fully at this point as eg M1 & M2 may be deemed to be excessive to spec.
If so, what is allowed?
eg are diodes OK - a diode switch could be implemented which is 'unblocked' by high or low output.
Here OA1 +ve output sing has to have Vout > Vhi + Vgsth of M1 and the opposite applies with M2.
Vin connection to IC1-+ input makes this look like negative hysteresis but M1/M2 may invert input polarities depending on how Vhi and Vlo are set. I have not fully thought through what the bounds are on the various voltages or even how they are best switched, but something along these lines looks workable.
simulate this circuit – Schematic created using CircuitLab
Why only one IC?
Being able to use two probably makes life more straightforward.
A diode gated version could look something like this.
Vlimhi and Vlimlo are either fed to point C via diodes D1 or D4 respectively or blocked by input from Vout via diodes D2 and D3.
R3 is a high value resistor shown as fed from Vdd/2 - but call this Vref instead. This resistor is intended to provide diode conduction of D1 and D4 when they are not blocked by Vout. Vref should lie about midway between the high and low limits and could be provided by a divider between them so it can move as they do. D1 & D4 should be Schottky diodes to minimise difference between the input voltages and opamp input. D1 & D2 maybe be silicon or Schottky.
Odds are that the circuit would need a little playing with to optimise it but it should work well enough for many purposes. I my have made some major error in polarity somewhere but hopefully not. Regardless, the principle should be clear enough.
In the circuit the waveforms at A B C D are all the same in polarity and shape but assume different levels as shown by the captions.
Resistor values are nominal.
R1 R2 stop the IC output fighting directly with the control voltages and R3 is intended to be >> R1 or R2 so reference voltages are not greatly diminished by resistor divider.
I've had to design this circuit in the past and what I opted for was two comparators and a D type flip flop. The upper threshold comparator clocked logical 1 into the flip flop and the lower threshold comparator reset the flip flop. It worked of course but I'm intrigued to see if there is a simpler (or more effective) solution.
Try using a microcontroller like the PIC12F675.
Not sure if you are this inclined or if your requirements allow it but it's something I did in the past for a simple sensor.
Use three of the ADC inputs, one for your signal and two for the thresholds and do your comparison and output activation in software.
Issues may include:
If one inverts the polarity of one of the comparators, one may use pair of NAND or NOR gates to build an RS latch; the outputs may then be treated as inverting and non-inverting Schmitt trigger outputs. On the other hand, like all latching circuits, there will be a danger that a signal which crosses the switching threshold of the upper comparator but never stays above it very long may generate runt pulses or another anomalies. If one would wish to condition a signal for use by a counter, a safer approach may be to generate a two-phase non-overlapping clock and then use latches rather than flip flops.
simulate this circuit – Schematic created using CircuitLab
The SO schematic editor is a little inconvenient, but the circuit below simulates a four-bit counter which will work cleanly even though the input is very noisy, provided that whenever the input brushes against the 4-volt threshold it must go solidly above 4 volts before the next time it brushes against the 1-volt threshold, and whenever it brushes against the 1-volt threshold it must go solidly below 1V before it brushes against the 4V threshold. Note that the phi1 and phi2 clocks generated by the comparators are themselves noisy, but such noise wouldn't matter even if it caused the latches to go momentarily metastable (the latches in this simulator don't do so even under extreme conditions, but real latches might) since any noise event that caused a latch to go metastable would be followed by a valid latching event.
