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In my lab, we successfully built a 4-bit binary parallel adder and were able to display the results of some tests on the 7 segment display.

But our TA asked us to try something: subtract 1-9, and we got 7. Why is that?

gbm0102
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2 Answers2

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So basically whenever you do 1-9 in binary that looks like

00001 (1) - 01001(9)

however since most of the subtraction is done by twos complement it is actually

00001 + 10110 => 10111

Your display will only display the bottom four bits which are 0111, which is seven.

Cheers!

zoder
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  • OP's system is 4-bit. Yours seems to be truncated 5-bit. Can you explain? – Transistor Oct 02 '17 at 22:16
  • I think that would depend on how the adder was made and implemented, as well as how was the subtraction performed. From my labs we did "adder implementations" in some sort of HDL with fpga's tied to them that could be a case, I really don't know how you would subtract -9 in a 4 bit implementation – zoder Oct 02 '17 at 22:19
  • @Transistor if you do what he did, for 4 bits, still the system only shows 0111 which is still 7. – parvin May 19 '19 at 15:49
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in binary:

1: 0001

Subtracting 9 times 1:

0000 (-1)
1111 (-2)
1110 (-3)
1101 (-4)
1100 (-5)
1011 (-6)
1010 (-7)
1001 (-8)
1000 (-9)

I would expect 1000, which is 8.

Michel Keijzers
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