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The MIPI I3C Basic standard describes an I2C-like bus with different timing requirements. In particular, that document describes a measure, tSCO, that describes a target device's clock-in to data-out responsiveness.

The maximum standard tSCO is 12 ns, but normally it is only 8 ns per Table 59. Both seem quite hard to implement in programmable synchronous logic, but I guess it makes sense for the I3C standard data rate of 12.5 MHz where the clock period gets down near 80 ns.

I3C can operate at slower clock speeds. My question is does it make sense that tSCO should scale with the clock speed?

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tim
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Burt_Harris
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  • No, not necessarily. Why would you want to violate the standard? – Elliot Alderson Dec 17 '20 at 22:00
  • As to why: In my initial experiment with a PSOC5LP UDB, the Cypress static timing checker indicated that the clock to output timing would be on the order of 23.635 ns, rather than 8-12. I'm doing some double-checking of the design I used for that, but for now it doesn't look like I can match the standard's default Tstp spec. – Burt_Harris Dec 18 '20 at 18:12
  • @tim - Hi, I note your recent edits to update older posts to the latest (Oct 2021) terminology of the I2C specification. Please stop making these updates for the time being. We need to get a consensus on Meta, including about what to do with historical posts, so I will post a new discussion topic on Meta soon. Thanks. – SamGibson Oct 25 '21 at 12:16
  • @SamGibson. No. It's not necessary. Why would you want to violate the standard? BTW: this question is about I3C and the standard is v1.1.1 of 2021-06-09. – tim Oct 25 '21 at 14:32
  • @tim - We are not going to discuss this here. Do not try to do so. Despite what may apply on other sites, on SE such decisions go through discussion on Meta. Any further attempts by you to edit related posts or discuss Meta issues here will be treated as site abuse. Please, please don't go there. As soon as I can post a reasonable starting point on Meta, I will do so. Thanks. – SamGibson Oct 25 '21 at 15:35

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