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I'm very confused on how to determine the equivalent circuit of this amplifier of common source in low amplitude signal mode. Any help is appreciated :

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toolic
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HellBoy
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1 Answers1

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The equivalent small-signal model will look exactly the same as if you would have used the NMOS.

schematic

simulate this circuit – Schematic created using CircuitLab

$$v_{in} = v_{gs} + i_dR_S = v_{gs} + g_m v_{gs} R_S = v_{gs}(1 + g_m R_S)$$

$$v_{out} = -i_d R_D = -g_m v_{gs} R_D$$

So the voltage gain is:

$$\frac{v_{out}}{v_{in}} = \frac{-g_m v_{gs} R_D}{v_{gs}(1 + g_m R_S)} = -\frac{g_m R_D}{1 + g_m R_S} = \frac{R_D}{\frac{1}{g_m} + R_S} $$

Or you could use this equivalent circuit if you do not like the idea that we have the same small signal model for PMOS and NMOS.

schematic

simulate this circuit

G36
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  • but where is the output resistance the one $r_0 = (\frac{\partial i_d}{\partial V_{SD}})^{-1} $ also why is this called common source where the source isnt connected to the ground? – HellBoy Oct 07 '23 at 21:26
  • I have added ro (output resistance) into schematics. We still call this CS because the input is at the gate and the output is at the drain. https://electronics.stackexchange.com/questions/295771/i-o-resistance-of-common-source-mosfet-with-source-degeneration/295966#295966 – G36 Oct 07 '23 at 21:38
  • why is $ r_0 $ connected that way shouldnt it have also its own ground link? – HellBoy Oct 08 '23 at 09:27
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    $r_o$ models the channel length modulation (Vds voltage due to channel length modulation will have a small effect on the drain current). Thus, $r_o$ is a resistance between the drain and the source terminal. https://electronics.stackexchange.com/questions/298829/common-drain-jfet-output-resistance-problem/299030#299030 – G36 Oct 08 '23 at 09:41
  • also since we have a PMOS in this case why did u write $ V_{GS} $ instead of $ V_{SG} $ ? – HellBoy Oct 08 '23 at 09:45
  • Why should I use Vsg if I can use the same small-signal model for NMOS and PMOS? What difference does it make? – G36 Oct 08 '23 at 10:07