Connecting a 3.3V circuit to a 5V bus

Question

I would like to connect a 3.3V (not 5V-tolerant) circuit (a Xilinx XC3S200 FPGA) to a TTL-level 5V asynchronous 16-bit bus (very similar to qbus) with about 30 mostly bidirectional lines. (The bus belongs to a Elektronika BK-0011 homecomputer with a 4 MHz KM1801VM1 CPU, similar to the LSI-11 CPUs).

I was thinking of using the simple FET bidirectional levelshifting circuit from NXP/Philips AN97055. Is this a good idea? What would be a good MOSFET to use? Many of them seem to have rather high input/output capacitances which could be an issue with rise times. Are there any other circuits worth considering?

The FPGA has configurable built-in pull-up resistors (about 3 kΩ) and the BK has 2.2 kΩ pull-up resistors on each line, can I omit the resistors in the level shifting circuit?

Answer 1

Bidirectional level shifting on a bus of this sort usually implies asking for trouble.

The note you linked to in your question talks about "I2C bus and similar systems", which basically means it's talking about open drain lines. This is usually NOT the case in wide high-speed parallel lines, where open drain is generally much too slow to be able to operate at those speeds. Both sides actually drive the bus.

You can take a look at TI's TXB0108 and that family of bi-directional drivers. These are the closest I have ever seen to what you want to do, but I have a feeling they will not work. Bidirectional busses such as this basically use the fact that the side that wants control of the line drives the bus lines harder than the buffer's output drive strength. In practice, with a parallel bus of this sort, that is unlikely to be the case. If memory serves, you need 2mA of drive strength on your IO lines on both sides for them to be override the buffer's output. This is not something you should assume to hold for your devices. In fact, I'd wager that just hooking up the lines pin to pin probably won't do the job.

In the real world, there really aren't many truly bidirectional buses. You should look carefully at your lines (you claim 30 lines for 16 bit wide bus - look carefully at the other 14). Many of those lines may not actually be birectional. Once you decide which side is the Master, and how the bus is laid out, it should actually be possible to specify the direction of most of those 14 lines. Further, using logic and a combination of those 14 lines, you should also be able to specify the direction of the 16 data lines. Use this signal, constructed from a logical combination of your control lines, to switch the direction of a regular level translating buffer. Many of them will switch fast enough to make it look like the translation is transparent. To be safe, I would suggest a small series resistor in series with all the lines to deal with possible race conditions in the switching - The output drivers of your IC's and those of the buffer will take different amount of time to respond, and unless you leave a lot of dead time in between you will see some bus contention. Series resistors will limit the current through the bus lines through these transients. Keep these resistors as low as possible, though, since they will limit the speed of the bus on their own.

Answer 2

I came across the ADG3300 while doing some research into level shifting. It has low gate capacitance, buffer propagation in the low tens of ns (and can run at 50Mbps with 5V/3V3), and requires no external parts other than bypass capacitors.

Answer 3

You can use a simple level translator, like this SN74LVC2T45 to achieve that.

If you are bringing only status lines, or a few low speed lines and have NFETs around (possibly elsewhere in your circuit, and you want to use the same part) you can use the following. The one downside is that it will burn some power (through the pull-up resistor) when the bus state is low. It also inverts the logic but you can compensate for that in an FPGA.

Your NFET's Vgs must be less than the lowest of the two system voltages, in this case lower than +3.3V

^{simulate this circuit – Schematic created using CircuitLab}