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I have a TTL-high output signal which I wish to use to send a negative pulse to a 28c256 EEPROM WE pin to write to it, but the high line may remain high until the next clock signal/output change etc. I don't really want to use an RC network because the EEPROM circuit already has one, and as things stand I only need to ground that RC subcircuit to execute a write by charging up the pin after 680ns or so.

I do understand how to use a 555 to generate a pulse but the circuits I have for that all rely on the trigger pulse/line being shorter than the output pulse, which I can't guarantee because of the constant high signal output by the glue logic. Obviously I am fine inverting any of the high output lines to achieve the target low pulse to the RC-write pin.

On a side note, how long does the ground need to be applied for the 680ns RC circuit (680ohm + 0.001F? cap). Specifically, could I simply use the TTL propagation delay of approx 19ns for the grounding of the RC signal? e.g. use a latch/flip-flop to produce the negative pulse somewhere in the circuit? Of course I need this only to fire once.

Is there a TTL chip out there to solve this problem easily?

Here is a diagram of the main points, and the 28c256 pinout: enter image description here enter image description here

The subcircuit to the left is the RC circuit, and as seen enables a button-press-to-write once the address and data lines are set. The youtube link for the specific video is here.

I know for a fact that the circuit can be modified to write using a clock signal ticking up through a 74HC193 chip and attached to a second 28c256 EEPROM, i.e. copying the contents of one EEPROM to another. The clock in that set-up was running at about 2Hz!!! Hope this last part helps.

Hektor
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  • From the question it isn't clear why the EEPROM WE pin seems to be controlled asynchronously from the device which is performing EEPROM accesses. Can the question be edited to include a schematic of all the connections to the EEPROM? – Chester Gillon Dec 16 '23 at 10:22
  • I don't yet have a schematic with all the connections, but the 28c256 pinout is now shown with a simplified version of the circuit, whose address and data pins are hard-wired for simplicity's sake, so it's pretty much the same circuit but with the intention of adding a line to the button subcircuit at the left, and thuis line will run to the right hand half of the switch, which on reflection I now uspect will possibly need some sort of resistor so that feeding the pulled-up 5V line with full-on TTL output won't mess with the RC draining. – Hektor Dec 16 '23 at 16:50
  • @ChesterGillon I think I see what you are asking. The reason the WE pin needs to be separated from the system clock is that the EEPROM writes can take up to 680ns, so a system clock of much above 1MHz would very likely lead to write cycles being interrupted once the glue logic-address decoder or master write signal were de-asserted. Thus I wanted to latch the signals involved with writing to the EEPROM to enable faster clock speeds without messing up EEPROM writes. – Hektor Dec 16 '23 at 17:28
  • The question is not clear. The input TTL signal has a positive-going leading edge and negative-going trailing edge. Irrespective of polarity, which edge do you want to use for the write enable? For example, do you want the incoming leading edge to immediately generate an negative-going Pulse of xxx ns? Or do you want a delay before the write pulse goes negative? Or . . .? – AnalogKid Jan 05 '24 at 22:54

2 Answers2

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I am not sure if I understand but try to look at circuit below. I works well if trigger high pulse is wider then output.enter image description here

Michal Podmanický
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After further searching, I came across this question, which seems to solve the issue, and using standard 74xx parts too. See zev hoover's answer using 2 d-type flip-flops. However, having now built the circuit, it seems to send a positive pulse every two clock cycles, which is not quite what I wanted, but at least sends a pulse when a constant high signal is applied to the input line, which I can work around.

As soon as the input line (at top left of each circuit diagram) goes high, a brief HIGH output pulse is sent, and then shortly afterwards the BAR-output of the second flip-flop switches high, and remains latched until the input signal is sent LOW again. (Apologies for the formatting, not very good with Photoshop)

The link to the simulation makes it clearer:

enter image description here enter image description here enter image description here

Simulation here

EDIT: ** Worth noting that this circuit repeatedly outputs its brief HIGH output signal, so strictly speaking isn't really a one-shot. **

Hektor
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