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Given n bits, for example, 00100110110001, there are six 1s in these bits.

I want to output 11111100000000, which moves the non-consecutive bit 1s to the left of the string.

I know some sequential logic can do this job, but sequential logic takes too much time.

I am wondering is there some low power and fast circuit to move non-consecutive bit 1s to consecutive bit 1s?

For example, is there some analog circuits or asyncronous circuits that can do this job?

In addition, the input signals are stored in a n-bit register, and the output signals are parallel signals. Moreover, the number of input bits is fixed. The number of input bits can be relatively large, e.g., n=128 or 256.

More importantly, is it possible to pack these bit 1s using some circuit which has the similar speed of a n-bit parallel counter but consumes less power than a n-bit parallel counter?

Voltage Spike
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Yu Qian
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    in this case sequential logic does not take time. Give more information on what you are expecting and if the output must be a parallel register or serial data. How are you intending to synchronize the input and output (fixed number of bits? signal for input or output available, ...) – Paul Ghobril Jan 16 '24 at 08:28
  • Thank you. Edited. – Yu Qian Jan 16 '24 at 08:35
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  • Any information on implementation? If one separate circuit, that's still in the hundreds of terminals. Don't know what current feasible CMOS fan-in and -out is - I doubt it reaches 256. – greybeard Jan 16 '24 at 08:47
  • Thank you very much. Sorting network is very inspiring! We can suppose input signals come from a 128-bit register, and output will be used for further process. And I also doubt the power consumption of a n-bit input sorting network may be larger than a n-bit parallel counter. – Yu Qian Jan 16 '24 at 08:51
  • @YuQian Question is way, way too broad. It includes analog, asynchronous (many may be unfamiliar with design techniques here), in addition to combinatorial. In addition to that, you broaden it out even further by sweeping under your tent the idea of packing. Way too wide a tent, my opinion. Divide it up. No one is writing your set of textbook chapters here. – periblepsis Jan 16 '24 at 09:09
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    @YuQian The obvious approach for lots of bits is to use CSA adder structures, grouping each set of three input bits. A straight-forward combinatorial approach for 3 bits might look like this. (Wire-OR can be applied.) But you've written nothing at all about what you have already considered and set aside, looking for better. I think you need to write a LOT MORE. And I think you need to narrow down the question, as well. Just my opinion. – periblepsis Jan 16 '24 at 09:37
  • What about the "time" for this ? – Antonio51 Jan 16 '24 at 10:51
  • The fastest digital logic would be to count the ones in the original word using a tree of full adders (requires O(log n) levels of logic), producing a binary number, and then use a binary-to-thermometer decoder (O(1) levels of logic) to produce the output word. – Dave Tweed Jan 16 '24 at 13:33
  • This will depend on a lot of things. How frequently does the input change? Do you need a solution that works asynchronously, or will a synchronous one do? Can multiple input bits change at the same time? If one bit changes from 0 to 1 at the same time that another one changes from 1 to 0, is it okay if one of the output bits briefly changes as a result? How much latency is acceptable? How much power consumption is acceptable? Would it be feasible to use an FPGA or do you need discrete components? – Tanner Swett Jan 17 '24 at 22:07

2 Answers2

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Use a "counter" that count the number of bits set and store that number N.
If you want write the bits sorted ... then write a bit 1 at left shifted N times right (If N > 0).
NB: it should be easy to make a circuit for a 8 or 16 bits wide.

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Antonio51
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If you feed the word into an analog bit counting circuit (an adder circuit), then you can give it to a LM3914 bar display driver that proportionally turns on channels based on the input voltage.

Jeroen3
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