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The attached image is a circuit using a rc-delayed (reset) signal to control a tristate gate (U855C).

After MPU_RESET is asserted, C852 starts charging. Gate U855D is always enabled. When the capacitor is chaged to roughly above 70% of Gate's VCC (1.8V), Gate D ouputs high and Gate C is disabled.

My question is, could I just connect RC to Gate C's OE_N pin directly, bypassing Gate D?

Theorectically, Gate C should be disabled when voltage at OE_N pin (pin 10) reaches about 30% of VCC (0.54V for 1.8V VCC), I can just tune the RC value to have a larger time constant.

Is there any pitfall to do this? The purpose is to save a gate for other usage.

using rc delayed signal to control a tri-state gate

matianfu
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  • Why would you be able to do it on gates A and B, but not on C? – Dave Tweed Aug 01 '20 at 10:09
  • Well, on gates A/B, the transition is fast. For Gate C, I am not sure whether the output is disabled when the voltage "leaving" LOW (~0.5V) or "entering" HIGH (~1.3V). I think it should behave in the former manner.What worries me is that the threshold voltage is "leaving LOW" and there are large variation among devices. Also considering the large tolerance variation of capacitor, these may translate into a large range of delay time. – matianfu Aug 01 '20 at 12:48
  • Yes, you can do what you describe. The addition of gate D doesn't really buy you any more accuracy. – td127 Aug 01 '20 at 19:48

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