A signalling standard typically used in buses that either drives the wire low, drives the wire high or disconnects from the wire (Hi-impedance, Hi-Z or tri-stated) such that there will not be a driver conflict when the wire is driven by another unit/driver. Two low impedance drivers driving to different levels (High Vs. Low) can potentially damage each other but certainly will corrupt the data on the wire. Allows for shared wires (with coordination).
Questions tagged [tri-state]
115 questions
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Tri State Buffer and Boolean Algebra
The basic operators of the boolean algebra are AND, OR, NOT. The modern digital circuits are based on this mathematical concept (Shannon's thesis, 1938).
I am wondering whether the Tri-State Buffer can be build (represented logically) with only…
u4783731
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Tri-State gates in CMOS
How do you build tri-state gates on transistor level? I've tried to come up with some designs -like connecting the output of the gate to the source port of a PMOS transistor with the enabled signal as its gate(base)- but it does not actually…
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using RC delay to trigger output enable pin of tri-state gate
The attached image is a circuit using a rc-delayed (reset) signal to control a tristate gate (U855C).
After MPU_RESET is asserted, C852 starts charging. Gate U855D is always enabled. When the capacitor is chaged to roughly above 70% of Gate's VCC…
matianfu
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How is the enable pin implemented in tri state logic?
I watched Ben Eater video on Youtube giving an introduction to tri state logic (https://m.youtube.com/watch?v=faAjse109Q8&t=98s).
He first presents a circuit made of two transistors (see picture)
He shows that depending on whether the top or bottom…
Winston
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Which case is better
if we want to construct 3 state inverter...
Which case is better? Having the enable near o/p or far the o/p
I have seen people drawing it far the o/p. But can't figure out why
Do you see? The upper inverter has the enable near the output. The lower…
KilGrave 09
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