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I was wondering how I can get Quartus to automatically generate VHDL IP from Qsys files, instead of the default Verilog.

I know I can change this in the command line or Platform Designer GUI for each Qsys block. However, I want to get it to work such that any designer using my project file doesn't need to open a lot of platform designer GUIs, to let the flow generate VHDL instead of Verilog.

I tried to change the following line in the Qsys files, but this does not look to have any effect:

<parameter name="hdlLanguage" value="VHDL" />

SamGibson
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Sebastiaan Mutsaards
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  • Do it via GUI for one block. 2) Examine logs to find exact command lines (or TCL commands or whatever) generated. 3) Hack command lines into a script to do all other blocks.
    • –  Dec 11 '20 at 14:38