Electrical Engineering Stack Exchange
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Questions tagged [quartus]

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Intel FPGA (formerly Altera).

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How do I generate a schematic block diagram from Verilog with Quartus Prime?

The answers to this question say that Altera Quartus will generate block diagrams from Verilog files. I'm a user of Quartus Prime Lite Edition. How do I generate block diagrams?
Ellen Spertus
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For a Quartus project what files must be added to a git repository?

A Quartus project generates huge number of files as we proceed with design compilation and debug automatically. Provided that I wish to add my Quartus project to a Git repository and not just the hdl files, what are the files that I must add? The…
quantum231
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Quartus keeps closing on me

Every time I create a new project quartus just closes on me. no error message no new window somewhere else it just closes. It makes the new project, and I can restart the program and work on the project. But when I try to compile the project I get…
Michael Hiltz
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What does symbol width and "beat" mean for Avalon-ST interface?

This is the GUI for the Avalon-ST Source BFM found in Quartus Platform Designer. I am trying to understand, what is the meaning of Symbol width and "beat" for streaming interface? The symbol width makes sense on a memory mapped bus where the…
gyuunyuu
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How to let Quartus generate VHDL out of Qsys automatically

I was wondering how I can get Quartus to automatically generate VHDL IP from Qsys files, instead of the default Verilog. I know I can change this in the command line or Platform Designer GUI for each Qsys block. However, I want to get it to work…
Sebastiaan Mutsaards
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I'm getting this error over and over and I don't know how to fix it . Error (12002): Port "S[0]" does not exist in macrofunction "inst8"

I'm working in Quartus 2, trying to use a busmux to select the what to do, but when I click compile I just get this error:
ignacio olveira
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How do you create a Platform Designer component with a parameterisable number of Avalon ST Ports?

I want to create a Platform Designer (PD) component that has a parameter which controls the number of Avalon ST ports (sinks and sources). I cannot find any documentation that explains what the HDL or _hw.tcl files should contain. I have created PD…
Robert Frisbee
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Why doesn't Qsys let me connect two conduits together by complaining that they do not have associated resets?

Error: MYSYSTEM.: Interfaces My_Design_0.to_debug_regs_conduit_out and DEBUG_REGISTERS_0.my_conduit_in must have matching associated resets, but My_Design_0.to_debug_regs_conduit_out has no associated reset. I have associated resets assigned in…
quantum231
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What is the proper method to become able to connect conduit signals inside Qsys?

Qsys (now known as Platform designer) identifies Avalon MM, Avalon ST, Clock, Reset and some other type of interfaces and makes it trivial to be able to connect them between different blocks. However, although I have read that conduits are not…
gyuunyuu
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What does "database" do in Quartus?

Quartus has settings to export/import database under the project drop-down box. The project directory contains two folders named db and incremental_db. What is this "database" and what does it contain?
gyuunyuu
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What is purpose of the "assignments" in the Qsys custom component editor signals and interfaces tab?

Here is the image showing what I am talking about, For Avalon Memory Mapped Slave port I can see that there are 4 options already there and they are already assigned custom values. I just want to know, what is the usage of this "assignments" when…
quantum231
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How can I edit my quartus project to work with relative paths?

I have a project in quartus with many files containing full-path-links to other files. I found a way to make it work on my machine with a different location, but that is the cheat way. I would like to change all the paths to be relative, so that…
Roman Chismar
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How to synthesis, fit, and generate assembly bistream without re-launch all proccess in Quartus?

In Quartus Prime (17.0) it take a looong time to generate bitstream on my computer. To generate the rbf for cycloneV, with DDR3 controller and serializer/deserializer in design it take about 12 minutes each time I modify a single parameter in…
FabienM
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