Error: MYSYSTEM.: Interfaces My_Design_0.to_debug_regs_conduit_out and DEBUG_REGISTERS_0.my_conduit_in must have matching associated resets, but My_Design_0.to_debug_regs_conduit_out has no associated reset.
I have associated resets assigned in both places. It must be noted that while the debug_regs has only one clock domain and thus a single reset, there are two clock domains in the my design and thus two resets.
EDIT:
In the Qsys system it can be seen that for one component the reset for clk_33 is connected to two resets, one for clk_33 and another for clk_132. For the other component, the reset is connected to clk_33 only. This is what generates the error. Now, if I connect the 2nd component's reset to two reset sources as well i.e one for clk_33 and another for clk_132, then the error message goes away.
What this means is that I just need to make sure that the reset signal on the two components is connected to the same reset sources. I am not sure why the person who created this Qsys system connected reset_33 (source) output to reset_33 and reset_132 inputs on the component and then also connected the reset_132 (source) output to reset_33 and reset_132 inputs on the component. It does look strange to say the least.