I want to create a Platform Designer (PD) component that has a parameter which controls the number of Avalon ST ports (sinks and sources). I cannot find any documentation that explains what the HDL or _hw.tcl files should contain.
I have created PD components that use HDL parameters to adjust the widths of interfaces, but not any that change the number of interfaces.
I looked at the Avalon-ST Multiplexer files that comes with PD and that uses an undocumented TCL command (altera_terp) that takes in a HDL template (.terp) file with embedded TCL-like sections that generates a customised HDL file based on the number of Avalon-ST sinks selected. Asking about documentation for the altera_terp command on the Intel FPGA forum has not provided any useful information, only a link to the PD documentation that doesn't explain how to do what I want to do!
Should the HDL be created with the maximum number of interfaces and the corresponding _hw.tcl file with commands that query the value of an HDL parameter to inform PD how to create termination logic for the unused interfaces?
If someone knows how to do this then a simple example (e.g. using a HDL parameter to adjust whether one or two Avalon-ST sinks are on a component) showing the relevant sections of the HDL and _hw.tcl files would be very helpful!
